Newsroom

May 16th, 2023

High Speed, Low Power and Flexibility Drive DisplayPort’s Increasing Popularity

In this article we provide an introduction to DP, talk about the various factors that IC designers will want to consider when integrating the DP functionality into their SOC, and present at a high-level the solutions Silicon Creations provides in this area.

March 21st, 2023

SOC Clocking Solutions Require Thought and Planning - Part 2

This is the second of two articles highlighting Silicon Creations. In this part, we will explore in more detail how Silicon Creations IP can be used to implement effective solutions that meet technical and business requirements.

March 1st, 2023

SOC Clocking Solutions Require Thought and Planning - Part 1

This is the first of two articles highlighting Silicon Creations. The second upcoming article will go into more detail on several scenarios showing how Silicon Creations IP is used to solve clocking challenges.

November 16th, 2022

Flexible Temperature Control Solution for Integrated Circuits Testing—Silicon Creations Thermal Elephant

Published in MDPI - November 2022 - Electronics Journals Volume 11 Issue 22

September 2nd, 2022

IEEE SSCS Poland Chapter Continues to Reach Out to the Young Generation of Designers

Published in IEEE Solid-State Circuits Magazine - Summer 2022

November 6th, 2021

PLL research at Auburn University supported by Silicon Creations

Published in: IEEE Journal of Solid-State Circuits ( Volume: 56, Issue: 3, March 2021)

May 21st, 2020

Why Do We Need SERDES?

Despite their design and verification complexity, SERDES have become an indispensable part of an SoC block. With SERDES IP blocks now available, it’s helped mitigate any cost, risk, and time-to-market escalation.

September 4th, 2019

IP’s Growing Impact On Yield And Reliability

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP.

June 27th, 2019

Test Chips Play Larger Role At Advanced Nodes

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production.

June 19th, 2019

Wrestling With High-Speed SerDes

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data.

May 30th, 2019

Why IP Quality Is So Difficult To Determine

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor.

November 10th, 2018

Any Silicon: CEO Talk with Randy Caplan from Silicon Creations

October 18th, 2018

Arm Musca-B1 test chip leads the way to develop secure IoT chip designs faster

February 18th, 2015

Silicon-Accurate Fractional-N PLL Design

January 10th, 2015

Is there a "one-size fits all" SOC PLL?