SOC Clocking Solutions Require Thought and Planning - Part 1
ChipEstimate Tech Talk with Jeff Galloway and Tom Simon — Silicon Creations
SOC Clocking Requirements
During the early stages of the design of a chip, time is viewed in the abstract. This applies equally for system clocks and for interface clocks. As the design moves from behavioral views to RTL, elements of time are added, but still in the form of ideal clock edges. When RTL moves to gates, the physical properties of the clock take on importance. Ideal clocks are replaced with real clock signals that must meet rigid requirements to ensure proper design functionality. Ideal clocks offer the luxury of not having to worry about jitter, duty cycle and the myriad of other physical challenges to clock signal integrity and SOC PPA. At the heart of any clocking scheme are the clocking elements such as crystal oscillators, free running oscillators, PLLs and CML buffers that provide the heartbeats of design.
About Silicon Creations
Silicon Creations is a self-funded, leading silicon IP developer with offices in the US and Poland, and sales representation worldwide. The company provides world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance SerDes and high-speed differential I/Os for diverse applications including smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices. Silicon Creations' IP is proven and/or in high-volume mass production in process technologies up to the most advanced available in the industry.
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