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Ring PLL

Silicon Creations Ring-PLLs are in mass production from 40nm to 180nm and proven in 28nm. Common features and benefits of our proven circuit architecture include:

- 24-bit Fractional modulator available providing frequency steps below 0.01ppm
- Fractional jitter compensation providing lower jitter than any other PLL IP
- Self-biasing circuit architecture tracks remarkably well over PVT giving predictable performance and high yields
- Simulation models with great silicon correlation accurately predict performance.

LC PLLs

In applications where ultra low jitter or phase noise is required, a high quality LC PLL is needed. Our fully integrated LC Tank based PLLs can achieve 20-60 times lower phase noise for a given power specification than a ring based PLL. This makes LC Tank based PLLs optimal for high performance applications such as wireless, high speed IO, or clocking of high resolution data converters.

Serializer – Deserializer IP

Our SerDes architecture has been proven in processes ranging from 180n to 28n. We specialize in low-power and Chip-chip interfaces, primarily up to 10Gb/s, including JESD204, XAUI, CPRI, SGMII, V-by-one, Infiniband and Serial RapidIO and for custom requirement.

LVDS-based IOs

Silicon Creations Bi-directional LVDS is silicon proven, fast (up to 3Gb/s) and highly programmable and with LVCMOS IOs on each pin is an excellent IO for FPGA to ASIC conversions. It is available as an IO, or a complete video interface with dynamic phase alignment meeting HDI, FPD Link, Camera Link, OpenLDI and other standards.