- In production from 180nm to 16nm, proven at 10nm and available beyond
- 24-bit Fractional modulator available providing frequency steps below 0.01ppm
- Fractional jitter compensation providing lower jitter than any other Fractional-N PLL IP
- Self-biasing circuit architecture tracks remarkably well over PVT giving predictable performance and high yields.
- Simulation models with great silicon correlation accurately predict performance.
- Isolated supply domains allow for excellent supply rejection in noisy SoC applications and shared supplies in less demanding applications.
- Fully integrated – no external components required. Minimal, or no additional supply decoupling required.
- Minimal to no keep-outs to adjacent circuits
- Loop bandwidth automatically adjusts for any input frequency, so no complicated programming is required.
Our Ring-PLL IP family includes:
- Fractional-N PLLs with a 24-bit delta-sigma modulator allowing the output frequency to be adjusted in steps smaller than 0.01ppm. The rich assortment of input, output and feedback dividers give this PLL an extremely wide operational range enabling software-controlled power-performance tradeoffs and allowing it to be used for many purposes ranging from digital and spread spectrum clocking to ADC clocking. Download a product overview.
- Extremely low area (e.g. 0.015mm2) ring PLLs running from core voltage only optimized for clocking digital circuits.
- High-speed, performance optimized integer PLLs with integrated jitter as low as 1ps RMS and suitable for clocking precision data converters and SerDes, yet using a fraction of the die area needed for an LC-PLL.
- Fully integrated Jitter Attenuator (jitter cleaner) PLLs optimized for Clock De-spreading, PON, OTU and Synchronous Ethernet applications.
- Multi-phase PLLs providing 12, 16 or even 32 outputs with accurately spaced phase suitable for phase alignment in source-synchronous data interfaces like DDR2, DDR3 and DDR4.
Click on pictures to enlarge.
Simulation models with great silicon correlation accurately predict performance.