Ring PLL

  • In production from 180nm to 10nm, proven at 7nm and available beyond
  • 24-bit Fractional modulator available providing frequency steps below 0.01ppm
  • Fractional jitter compensation providing lower jitter than any other Fractional-N PLL IP
  • Self-biasing circuit architecture tracks remarkably well over PVT giving predictable performance and high yields.
  • Simulation models with great silicon correlation accurately predict performance.
  • Isolated supply domains allow for excellent supply rejection in noisy SoC applications and shared supplies in less demanding applications.
  • Fully integrated – no external components required. Minimal, or no additional supply decoupling required.
  • Minimal to no keep-outs to adjacent circuits
  • Loop bandwidth automatically adjusts for any input frequency, so no complicated programming is required.

Our Ring-PLL IP family includes:

  • Fractional-N PLLs with a 24-bit delta-sigma modulator allowing the output frequency to be adjusted in steps smaller than 0.01ppm. The rich assortment of input, output and feedback dividers give this PLL an extremely wide operational range enabling software-controlled power-performance tradeoffs and allowing it to be used for many purposes ranging from digital and spread spectrum clocking to ADC clocking. Download a product overview.

  • IoT PLLs for ultra-low power applications using microwatts of power when operating, 32.768kHz reference clocks and with extremely fast start/stop times.

  • Deskew PLLs for DDR interfaces and Zero-delay buffer applications.

  • Extremely low area (e.g. 0.015mm2) ring PLLs running from core voltage only optimized for clocking digital circuits.

  • High-speed, performance optimized integer PLLs with integrated jitter as low as 1ps RMS and suitable for clocking precision data converters and SerDes, yet using a fraction of the die area needed for an LC-PLL.

  • Fully integrated Jitter Attenuator (jitter cleaner) PLLs optimized for Clock De-spreading, PON, OTU and Synchronous Ethernet applications.

  • Multi-phase PLLs providing 12, 16 or even 32 outputs with accurately spaced phase suitable for phase alignment in source-synchronous data interfaces like DDR2, DDR3 and DDR4.

This email address is being protected from spambots. You need JavaScript enabled to view it.

Click on pictures to enlarge.

Simulation models with great silicon correlation accurately predict performance.

Fractional-N Ring PLL
Fractional-N Ring PLL



Multiphase (DDR) Ring PLL
Multiphase (DDR) Ring PLL



Jitter Optimized Ring PLL
Jitter Optimized Ring PLL

Silicon IP

Silicon Creations is a leading silicon IP developer with offices in the US and Poland. The company is focused on providing world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), low power, high-performance SerDes and high-speed differential I/Os. Silicon Creations' IP is proven from 7 to 180-nanometer process technologies. Please visit our products page to learn more about our products. 

With a complete commitment to customer success, our IP has an excellent record of first silicon to mass production in customer designs. Our team would be delighted to meet with you and help solve your ASIC and SoC challenges. To contact us or one of our sales representatives please visit our contacts page.


This email address is being protected from spambots. You need JavaScript enabled to view it.


Corporate Headquarters:
1745 North Brown Rd, Suite 200
Lawrenceville, GA 30043


P (local): 678-259-9301
P (US Toll-Free): 866-232-3431
F: 678-259-9301


Contact Us