Silicon Creations VP & Co-Founder, Randy Caplan, was recently interviewed by SemiWiki for their popular "CEO Interview" series.
Andrew Cole, VP of Business Development at Silicon Creations gave an interview at the September 2016 IPSoC event in Shanghai. Click here to view the interview.
Mentor On Demand Seminar “Design and Circuit Verification Challenges of a 250Mbps to 12.7Gbps Multiprotocol SerDes PMA” by Jeff Galloway at Mentor User2User in April, 2016. Click here to view the presentation.
Silicon Creations gave a talk at the September 2015 IPSoC event in Shanghai. The presentation is about a problem we at Silicon Creations have seen quite often when our, or others’ PLLs are used in complex SoCs. Although the design team usually implements the PLL correctly in the chip with the right supplies connected the right ways, we have often seen that designers overlook the significant impact that their floorplan and power supply plan have on the clock as it travels from the PLL to the circuits the PLL is clocking. This is the impact of the SoCsupply noise on the quality of the clock. Click here to view this paper.
Silicon Creations gave a talk at the September 2015 IPSoC event in Shanghai. The presentation describes our experiences in porting designs from 180nm CMOS though 16nm and 10nm FinFet processes. Some key figures of merit are shown comparing the processes. Click here to view this paper.
A simple yet high performance time-to-digital converter (TDC) architecture is proposed in this paper. Its key advantage is its ability to sample-and-hold a time interval and thereafter oversample the stored quantity to provide sub-gate delay resolution and high linearity. The converter is fully digital, synthesizable from standard logic cells, and owes its properties to the time storage mechanism which relies on injecting more than one signal edge into a ring oscillator and tracking their relative angle. Results from a prototype on FPGA reveal excellent noise suppression by achieving a single-shot precision of 0.05 times the unit inverting logic cell delay in the ring oscillator by using an oversampling ratio of 64. Click here to view this paper.
An all-digital phase locked loop (ADPLL) that uses a second fractional-N PLL as its digitally-controlled oscillator (DCO) has been studied, prototyped and tested. This technique allows for an effective implementation of a low-bandwidth ADPLL, exploiting the benefits of a digital implementation while avoiding the complexity of designing a DCO and a Time-to-digital converter (TDC). The reuse of a PLL as a DCO provides for easy interfacing, high linearity, zero drift and very high frequency resolution. An overview of the theory, technique, limitations, applications, and results are presented in this paper.
Silicon Creations gave a talk titled "Supply Noise-Induced Jitter and Its Impact on Timing Margin" at the Cadence Mixed-Signal Technology Summit 2014 in San Jose, California. This paper provides extensive information on the various kinds of jitter that come from PLLs, what is important for various applications, how supply noise in SoCs can cause jitter in PLL output stages and clock trees, and how to estimate, simulate and manage this jitter.
Silicon-Accurate Fractional-N PLL Design, paper by Andrew Cole, Silicon Creations at IPSoC, Grenoble France– (12/4/2012)
EDN, December 2010: http://www.edn.com/design/analog/4363864/SOC-PLL-design-requires-trade-offs
EDN, July 2011: http://www.edn.com/design/analog/4368208/Tracking-PLL-design-through-the-decades-part-1
ChipEstimate, August 2011: http://www.chipestimate.com/tech-talks/2011/08/30/Silicon-Creations-Tracking-PLL-Design-Through-the-Decades
Berkeley Design Automation white paper: http://www.berkeley-da.com/prod/datasheets/White_Paper_Silicon_Creations_AFS_fnl.pdf
Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International, 2012. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6258342&contentType=Conference+Publications.