Publications Xplore Digital Library

– (1/9/2018)

Time-to-DIgital Converter With Sample-and-Hold and Quantization Noise Scrambling Using Harmonics in Ring Oscillators.

A high-resolution, high-bandwidth, and noise-scrambling, time-to-digital converter (TDC) is presented. Its architecture, which exploits harmonics in ring oscillators, provides a sample-and-hold mechanism in the form of relative phase. This storage mechanism is highly insensitive to noise and allows for oversampling between input events, therefore, can be designed for very high bandwidth. It can achieve lower quantization noise with fewer measurements than noise-shaping TDCs. This paper presents the architecture in detail, an in-depth analysis of noise sensitivity of the time storage mechanism, and the results from a prototype implemented in a 28-nm CMOS process.
Date of Publication: 20 June 2017 


Safety qualification for leading edge IP elements - presentation at REUSE 2017 in Santa Clara

– (12/6/2017)

Silicon Creations VP, Andrew Cole presented a talk on "Safety qualification for leading edge IP elements" at REUSE 2017 in Santa Clara.

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See SemiWiki's summary of the presentation

Other articles on Silicon Creations on SemiWiki


SemiWiki - Silicon Creations talks about 7nm IP Verification for AMS Circuits

– (10/24/2017)

SemiWiki: Designing at 7nm is a big deal because of the costs to make masks and then produce silicon that yields at an acceptable level, and Silicon Creations is one company that has the experience in designing AMS IP like: PLL, Serializer-Deserializer, IOs, Oscillators. 

Read the full article.

Other articles on Silicon Creations on SemiWiki

High-Performance 7nm IP Verification with the AFS Platform At Silicon Creations

– (9/27/2017)

How one company achieved first-pass silicon for a mixed-signal design.

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Advanced PLL and Multi-Protocol SerDes Technology

– (9/2/2016)

Andrew Cole, VP of Business Development at Silicon Creations gave an interview at the September 2016 IPSoC event in Shanghai.  Click here to view the interview.

SerDes Design Challenges

– (4/26/2016)

Mentor On Demand Seminar “Design and Circuit Verification Challenges of a 250Mbps to 12.7Gbps Multiprotocol SerDes PMA” by Jeff Galloway at Mentor  User2User in April, 2016.   Click here to view the presentation.


Supply Noise Induced Jitter - Don't Let it Kill your Chip

– (10/11/2015)

Silicon Creations gave a talk at the September 2015 IPSoC event in Shanghai. The presentation is about a problem we at Silicon Creations have seen quite often when our, or others’ PLLs are used in complex SoCs. Although the design team usually implements the PLL correctly in the chip with the right supplies connected the right ways, we have often seen that designers overlook the significant impact that their floorplan and power supply plan have on the clock as it travels from the PLL to the circuits the PLL is clocking. This is the impact of the SoCsupply noise on the quality of the clock.  Click here to view this paper.

Experiences and Benefits of 16nm and 10nm FinFet Development

– (10/12/2015)

Silicon Creations gave a talk at the September 2015 IPSoC event in Shanghai. The presentation describes our experiences in porting designs from 180nm CMOS though 16nm and 10nm FinFet processes. Some key figures of merit are shown comparing the processes.  Click here to view this paper.

Harmonic ring oscillator time-to-digital converter

– (5/24/2015)

A simple yet high performance time-to-digital converter (TDC) architecture is proposed in this paper. Its key advantage is its ability to sample-and-hold a time interval and thereafter oversample the stored quantity to provide sub-gate delay resolution and high linearity. The converter is fully digital, synthesizable from standard logic cells, and owes its properties to the time storage mechanism which relies on injecting more than one signal edge into a ring oscillator and tracking their relative angle. Results from a prototype on FPGA reveal excellent noise suppression by achieving a single-shot precision of 0.05 times the unit inverting logic cell delay in the ring oscillator by using an oversampling ratio of 64. Click here to view this paper.

A phase locked loop used as a digitally-controlled oscillator for flexible frequency synthesis

– (4/13/2015)

An all-digital phase locked loop (ADPLL) that uses a second fractional-N PLL as its digitally-controlled oscillator (DCO) has been studied, prototyped and tested. This technique allows for an effective implementation of a low-bandwidth ADPLL, exploiting the benefits of a digital implementation while avoiding the complexity of designing a DCO and a Time-to-digital converter (TDC). The reuse of a PLL as a DCO provides for easy interfacing, high linearity, zero drift and very high frequency resolution. An overview of the theory, technique, limitations, applications, and results are presented in this paper.

Silicon-Accurate Mixed-Signal Fractional-N PLL IP – TSMC Open Innovation Platform (OIP) Ecosystem Forum, San Jose

– (10/16/2012)

Joint paper with Berkeley Design Automation; received the Customer's Choice Award; Location Here. (A TSMC-Online account is required to view the paper.)

Silicon IP

Silicon Creations is a leading silicon IP developer with offices in the US and Poland. The company is focused on providing world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), low power, high-performance SerDes and high-speed differential I/Os. Silicon Creations' IP is proven from 7 to 180-nanometer process technologies. Please visit our products page to learn more about our products. 

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